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Si5040
Register 8. RxCalConfig
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
hardRecal
VCOCAL[1:0]
swReset
Type
R
R
R
R
R/W
R/W
R/W
R/W
Reset settings = 0000 0000
Bit
7:4
3
2:1
0
Name
Reserved
hardRecal
VCOCAL[1:0]
swReset
Function
Read returns zero.
Force Recalibarions.
0 = Normal operation
1 = Initiate all calibrations of internal circuits and do not reset all RX registers. Bit is
cleared upon completion of calibrations.
Receive VCO Calibration Modes.
00 (Default) = Automatic detection of the reference clock is enabled. If the reference
clock is present and rxRefclkEn (Register 7, bit 0), it will be used to center the internal
VCO pull range at the beginning of the lock acquisition process. Otherwise, the entire
VCO frequency range will be swept.
01 = Enable referenceless operation. The entire VCO frequency range will be swept dur-
ing the CDR lock acquisition process regardless of the presence of the reference clock.
10 = Enable reference operation. The internal VCO pull range will be centered with the
reference clock frequency.
11 = Invalid mode. Note that receive LOL will always be on.
Note: VCOCAL[1:0] must be set to reference (10b) or auto mode (00b) when part is configured to
be in XFI loopback mode.
Note: When Rx VCOCAL = x0b and a valid reference clock is present and rxRefclkEn = 1
(reg7[0]), registers 77 and 98 must not be written to. See section “5.8.1.1. Dynamic
Register Control”.
Reset.
0 = Normal operation.
1 = Reset all RX side registers. Bit is cleared upon completion of reset.
Rev. 1.3
51
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